Chips
| Show | Chip | Mac models | Datasets | Status | Core types |
|---|
Tick two or more chips to compare them side by side.
What the labels mean
- Accepted
- The dataset passed every automatic check: format and privacy, tool version, statistics
recomputed from the per-run values, the physical anchors (add takes 1 cycle, a compare
feeding
csinc 2, nothing faster than the core is wide), internal consistency, and
agreement with the other datasets of the same chip. A maintainer then merged it.
- Flagged
- The dataset passed the hard checks, but more than 0.5 % of its values
differ from the chip's other datasets by more than run-to-run noise explains. It is
published because a maintainer looked at it, and the chip's figures leave its outlying
values out.
- Marked value †
- At least one dataset of this chip disagrees on this value. The figure shown is the median
of the datasets that agree; open the row to see each one.
- Verified chip
- At least two independent submissions (separate issues or pull requests) were accepted
and agree. The automatic checks catch mistakes and naive forgery; they cannot stop someone
determined to fabricate consistent data. Independent submissions are the real defence,
which is why every chip shows how many it has.
- Single submission
- One accepted dataset: checked, but not yet reproduced by anyone else.
How to read the tables
- Latency is in cycles, from one input operand to the output, measured in a
dependency chain. When inputs differ, the cell shows the range; open the row for each one.
A value near 0 means the instruction was removed at rename.
- Throughput is how many independent instances complete per cycle in a long stream
of that one instruction. * means the stream was limited by its
own dependency chain, so the figure is a latency, not a unit count.
- Values are medians: of the runs for one dataset, and of the datasets when a chip has
several. Non-integer latencies are real averages, not rounding noise.
- rt marks a round trip: the chain had to return to its starting register file
through a second instruction (named in the row) whose share cannot be separated by timing.
- Without root there are no event counters. Everything except cycles and retired
instructions is inferred from timing experiments; open a structure row to see the curve it
was read from.
Core structure
Figures in the last column are quoted from the sources below; they were not measured by this tool, and definitions differ slightly (see each source).
Datasets
Every dataset links to where it came from, and to its data file. Open a row to see the values marked against the other datasets.
| Chip | Dataset | Mac | macOS | Tool | Runs | Load avg. | Status | Source |
|---|